1. Field of the Invention
The present disclosure relates generally to packet network packet processors, and more particularly to memory systems and access methods for such processors.
2. Description of Related Art
Data packets (also called “frames” in some scenarios) placed on a packet-based network generally pass through one or more packet switches and/or routers as the packets traverse between the packet source and packet destination(s). Each switch/router receiving such a packet examines one or more headers on the packet to decide what processing tasks must be performed on the packet, and the appropriate egress interface(s) that the switch/router should use to forward the packet toward its destination(s). It is desirable that each switch/router process packets quickly, so as to reduce packet latency and avoid having to drop packets.
High-performance packet routers and switches use dedicated packet network packet processors to handle packets. FIG. 1 depicts a simplified view of a system 100 including a packet processor 110. Ingress buffers (not shown) internal and/or external to packet processor 110 queue packets received by one or more switch/router interfaces and awaiting processing by the packet processor. Egress buffers (also not shown) internal and/or external to packet processor 110 hold packets subsequent to processing by the packet processor and queued for forwarding out an appropriate switch router interface or interfaces.
Packet processor 110 typically must handle packets from many different source/destination pairs, and packets of many different types. Depending on these variables, different packets require different lookups and different processing. Lookup information is stored in tables in a memory accessible to the packet processor, e.g., memory 120 made up of two memory devices 120-0, 120-1. Each memory device can be one of the familiar solid-state memory device types, such as a Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Flash memory, etc. In FIG. 1, each memory device is a 1 Mb×72-bit SRAM. Packet processor supplies an address signal to memory devices 120-0, 120-1 over 20 address lines A[0:19] (well-known control signals are also supplied over separate command lines, not shown). Data passes between each memory device and packet processor 110 over 72 dedicated data lines (DQ[0:71] and DQ[72:143] for memory devices 120-0 and 120-1, respectively). Thus in operation, devices 120-0 and 120-1 appear as one large 144-bit-wide memory. Various tables needed for packet processor operation are stored in different partitions of the memory.
The prior art packet processor/memory configuration is limited in the manner in which table information can be retrieved. For instance, if five tables must be accessed to retrieve five types of information for processing a packet, five separate accesses are required. For line rate processing of small packets, packet processing requiring many table read operations can quickly overwhelm the memory system, resulting in delays and undesired packet dropping to avoid buffer overflow.